Phase lock loop circuits (PLLs) are electronic control circuits that are widely employed in radio, telecommunications, computers and other electronic applications. A few common applications of PLLs include signal demodulation, signal recovery from a noisy channel, generation of a stable frequency at multiples of an input frequency (frequency synthesis), and distribution of precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices. These circuits can produce output frequencies from a fraction of a hertz up to many gigahertz.
FIG. 6 depicts an arrangement of functional units in a prior art digital PLL 600 that is configured to generate a higher frequency output signal with reference to a lower frequency input signal. The PLL 600 includes phase detector/phase frequency detector 608, a low-pass loop filter 612, voltage controlled oscillator (VCO) 616 and a frequency divider 620. An external frequency generator produces a reference input signal 604 that is applied to an input of the phase detector 608. The output of the phase detector passes through a loop filter 612 and the filtered output operates the VCO 616. The VCO 616 accepts an analog control signal in the PLL circuit 600. A digital to analog converter (DAC) 614 generates an analog signal corresponding to a digital output signal from the loop filter 612. In the PLL circuit 600, a sigma-delta modulator 613 receives the filtered digital control signal from the loop filter 612 and generates a high frequency dithered control signal output for the input of the DAC 614. The VCO 616 generates an output signal 640, which is passed to a frequency divider 620 and the output of the frequency divider 620 provides feedback to the phase detector 608. In many embodiments, the phase detector 608 is a multiplier that produces a product of two signals to downconvert an input signal to another signal with low frequency that is close to DC. The VCO 616 is tuned to a range of frequencies corresponding to the higher frequency harmonic so the output of the PLL 640 is a higher frequency multiple of the input reference signal 604.
The phase detector 608 identifies differences in phase between the input reference signal 604 and the output of the PLL 600. In situations where the PLL 600 is generating a multiplied frequency output, the higher frequency output signal 640 would not correspond to the lower-frequency input signal 604. The frequency divider 620 receives the higher frequency output 640 and generates a lower frequency output at the same frequency as the input reference signal 604 for the phase detector 608. The phase detector 608 identifies deviations between the phase of the output signal from the frequency divider 620 and the input reference signal 604. If the input reference signal and feedback signal are locked in phase, then the two signals are orthogonal to one another (separated by 90°). The phase detector 608 generates a corrected output signal in response to any errors between the phases of the input and output signals. Thus, the PLL circuit uses a negative feedback loop to correct phase differences between the input reference signal and an output signal.
In the PLL circuit 600, the DAC 614 generates an analog output that controls the VCO 616 to generate a signal for the feedback divider 620. In one embodiment, the DAC 614 is a sigma-delta modulator that generates an analog version of the digital control signal from the loop filter 612.
The DAC 614 can generate a comparatively limited number of distinct output levels, which is typically expressed as 2M levels for a DAC with M bits of resolution. For example, a 4-bit DAC generates 16 distinct output levels. In many instances, control of the VCO 616 requires greater precision than 16 control levels, so the DAC 614 receives a digital control signal that switches between different digital values at a high frequency to enable the DAC 614 to generate the analog control signal at average levels that are between the limited number of discrete output levels for the DAC 614. This high frequency operation of the DAC 614 in response to the dither signal from the sigma-delta modulator 613 is known as dithered operation. During dithered operation, the output from DAC 614 changes between distinct output levels in response to the dithered digital control signal from the from the sigma-delta modulator 613. The sigma-delta modulator 612 dithers the digital control signal from the loop filter 612 at a high frequency, such as ¼th the frequency of the output signal from the VCO 616, and the DAC 614 switches output levels rapidly with reference to the dithered control signal. The rapid switching between output levels for the output of the DAC 614 produces a range of control signals that include intermediate values between the comparatively limited number of discrete output levels for the DAC 614, and enables detailed control of the VCO 616. The dithering process generates quantization noise in the control signal that is applied to the VCO 616. Since the dithering of the output from the DAC 614 occurs at a high frequency, the dithering noise has minimal negative impact on the control signal for the VCO 616, which typically has a low frequency band that includes 0 Hz (DC).
While the dithered output signal of the DAC 614 is generated with a high frequency that is suitable for use with the VCO 616, the feedback divider 620 shifts the quantization noise from the DAC 614 down to lower frequencies that potentially interfere with the operation of the PLL because the feedback divider 620 suffers from aliasing while sampling the output signal from the VCO 616. FIG. 7 depicts the low frequency noise in more detail. In FIG. 7, the timing diagram 704 depicts an ideal high-frequency output signal from the VCO 616 that is provided as input to the divider 620. The timing diagram 708 depicts an actual output from the VCO 616 that includes quantization noise components from the DAC 614. The quantization noise manifests as jitter in the periods and phase of the high-frequency output signal 708. The divider 620 usually samples the noisy output signal 708 at a frequency lower than the DAC frequency to generate a lower-frequency divider output signal 712. For example, in FIG. 7 the divider 620 samples the noisy signal 712 at ¼th the frequency of the output signal from the VCO 616 in the PLL circuit. Due to aliasing that occurs when sampling at ¼th of the frequency of the output signal from the VCO 616, the divider 620 aliases the quantization noise in the high-frequency signal 708 in the lower-frequency feedback signal 712. As depicted in the graph 724, the quantization phase noise at the high-frequency output of the VCO 616 mostly occurs at high-frequencies with low quantization noise levels near 0 Hz (DC). However, the operation of the divider 620 shifts or “folds back” the quantization noise to lower-frequencies. The graph 728 depicts large portions of the quantization noise around ¼ and ½ of the frequency felk from the VCO 616 are shifted down to the felk/8 frequency to increase the DC quantization noise level 732 at that range.
In prior art PLL circuits, one method to reduce the effects of the quantization noise in the divider is to reduce the gain of the VCO 616. However, reducing the gain of the VCO 616 also makes the PLL circuit 600 less effective at maintaining a lock on the reference signal in the presence of drift and other variations in the reference signal. Consequently, improvements to PLL circuits that reduce low-frequency quantization noise would be beneficial.